Electronic calculator systems of the type wherein all the main electronic functions are integrated on a single integrated semiconductor chip wherein a small number of such chips are described in the following U.S. Patents, which are assigned to the assignee of this invention:
U.s. pat. No., 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "Calculator System Having An Exchange Data Memory Register", PA1 U.s. pat. No. 3,934,233 issued to Roger J. Fisher and Jerald D. Rogers on Jan. 20, 1976 and entitled "Read-Only-Memory for Electronic Calculator", PA1 U.s. pat. No. 3,931,507 issued to George L. Brantingham on Jan. 6, 1976 and entitled "Power-Up Clear in Electronic Digital Calculator", PA1 U.s. pat. No. 3,988,604 issued to Joseph H. Raymond, Jr. on Oct. 26, 1976 and entitled "Electronic Calculator or Digital Processor Chip Having Multiple Function Arithmetic Unit Output".
The concepts of these prior applications have made possible vast reductions in the cost of the small personal-sized calculators. Continuing efforts to reduce the cost of these products include the development of a calculator chip utilizing minimum semiconductor chip area and which is capable of performing addition, subtraction, multiplication, division, squaring, square rooting, percent and memory operations. The chip disclosed herein may be utilized in hand-held or desk model calculators capable of performing operations of the aforementioned types and may be implemented on a very small semiconductor chip.
The present invention relates to a selectively loadable instruction register system for a microprocessor and more specifically a selectively loadable instruction register system for an electronic calculator implemented on a semiconductor chip. An entire electronic calculator system which utilizes the selectively loadable instruction register system of this invention is disclosed. The electronic calculator system disclosed in a serial, word organized calculator; however, the invention is not limited to this type calculator, but rather may be utilized in microprocessors generally.
In the prior art, it has been known to use an instruction word register, such as that disclosed in U.S. Pat. No. 3,919,532 where the instruction words stored in the instruction memory, e.g. the read-only-memory, are invariably outputted to the system's instruction register. Also in the prior art, as exemplified by U.S. Pat. No. 3,934,233, an instruction register may be selectably loadable from the read-only-memory, but this was done only to permit the program counter to be used as a time-out counter. In U.S. Pat. No. 3,934,233 the only instruction word decoded is the instruction word outputted from the instruction register. Further, in the prior art, as exemplified by U.S. Pat. No. 3,988,604, instruction registers has been eliminated so that the instruction word outputted from the read-only-memory is decoded by various decoders locally.
It has been found that by using an instruction register which is selectively loadable from the read-only-memory and using decoder circuits, some of which are responsive to the instruction word outputted directly from the instruction memory and others of which are responsive to the instruction word outputted from the instruction register, it is possible to simplify the decoders responsive to the instruction word outputted from the instruction register if certain types of instructions are not loaded therein. By simplifying the decoders responsive to the instruction word outputted from the instruction register, such decoders require fewer gates to be implemented and they then require fewer conductors to provide them with the instruction word in the instruction register. This then reduces the size of the semiconductor chip needed to implement a calculator or microprocessor system.
It is therefore one object of this invention to provide a selectively loadable instruction register system permitting more efficient use of chip silicon area.
It is another object of this invention to provide a selectively loadable instruction register, the instruction register being loaded from an instruction memory depending on the state of selected bits of the instruction words outputted therefrom. It being another object to provide decoder circuits responsive to the instruction word outputted from the instruction memory and from the instruction register.
It is still another object of this invention to improve the instruction registers and decoder logic circuits associated therewith an electronic calculators and microprocessors systems.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, an electronic microprocessor or calculator system having a data memory, an arithmetic unit for performing arithmetic operations on numeric data stored in the data memory, an instruction memory for storing a plurality of instruction words, the instruction words controlling the operation of the system, and a program counter for addressing the instruction memory, is provided with a selectively loadable instruction register as associated decoder logic circuits. A first decoder logic circuit, responsive to at least a portion of each instruction word outputted from instruction memory, is provided for generating an enabling signal for selected ones of the plurality of instruction words outputtable from the instruction memory. The enabling signal generated by the first decoder logic circuit permits the instruction word outputted from the instruction memory to be temporarily stored in an instruction word register. Second and third decoder logic circuits are provided, the second logic circuits decoding the aforementioned selective ones of the plurality instructions loaded into the instruction word register and the third decoder logic circuit decoding instruction words outputted from the instruction memory. Preferably, the instruction word register is enabled by the enabling signal to temporarily store instructions for transferring data within the data memory and for transferring data between the data memory and the arithmetic unit, but is not loaded with instruction words for performing branch operations, for instance. Also, the instruction register is preferably automatically loaded with a no-operation instruction when not loaded with the instruction word outputted from the instruction memory.